In the field of integrated semiconductor circuits the ever-smaller minimal structural dimensions of the respective circuit elements pose ever-higher demands on the production processes of integrated semiconductor circuits. To the same extent the demands on the so-called chip performance also increase. For this reason it is tried to already take account of process variations unavoidable in practice, if possible, in the circuit simulation of the integrated semiconductor circuit. This results in interval regions for the chip performance, within which the chip performance should typically be. With this modified circuit simulations, however, the velocity variations of the integrated semiconductor circuits, really occurring during the production of same, due to process variations naturally cannot be predicted exactly. Thus it is typically required that, when, on the one hand, large intervals for the respective chip performance are present and, on the other hand, high customer demands are posed on the integrated semiconductor circuits, each semiconductor circuit, i.e. each individual chip, would have to be subjected to a test for examining the chip performance.
In practice, however, the performance, i.e. the velocity or the signal delay, respectively, of the integrated semiconductor circuits produced is manually examined at a few selected semiconductor circuits. This manual examination, however, on the one hand requires lots of personnel and on the other hand, as expected, does not cover the entire process window, i.e. the predetermined velocity interval.
In addition the personnel required for the examination of the chip performance contributes considerably to the production cost of semiconductor circuits. Since, as has been mentioned above, only a certain selection of the semiconductor circuits produced is examined, no final and comprehensive statements about the chip performance of all the integrated semiconductor circuits produced can be made.